/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Mcu_Rstgen.h                                                                              *
 *  \brief    This file contains interface header for MCU MCAL driver, ...                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/08/02     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef MCU_RSTGEN_H
#define MCU_RSTGEN_H
/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Mcu_GeneralTypes.h"

/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/

#define DOM_PER0_OFF(n)  (0x0U + 20U*(n))

#define DOM_PER1_OFF(n)  (0x4U + 20U*(n))

#define DOM_PER2_OFF(n)  (0x8U + 20U*(n))

#define DOM_PER3_OFF(n)  (0xcU + 20U*(n))

#define DOM_PER_LOCK_OFF(n)  (0x10U + 20U*(n))

#define GLOBAL_RESET_RS_OFF  0x200U

#define BM_GLOBAL_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_GLOBAL_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_GLOBAL_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_GLOBAL_RESET_RS_RS)
#define GFV_GLOBAL_RESET_RS_RS(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_RS_RS) >> 1U)

#define BM_GLOBAL_RESET_RS_EN  ((uint32)0x01U << 0U)

#define GLOBAL_RESET_CONTROL_OFF  (0x204U)

#define BM_GLOBAL_RESET_CONTROL_SS_RDY  ((uint32)0x01U << 31U)

#define BM_GLOBAL_RESET_CONTROL_TEST_IST_EN  ((uint32)0x01U << 29U)

#define BM_GLOBAL_RESET_CONTROL_SW_GLB_RST  ((uint32)0x01U << 28U)

#define BM_GLOBAL_RESET_CONTROL_SW_GLB_RST_EN  ((uint32)0x01U << 27U)

#define FM_GLOBAL_RESET_CONTROL_RST_REQ_EN  ((uint32)0xffU << 19U)
#define FV_GLOBAL_RESET_CONTROL_RST_REQ_EN(v) \
  (((uint32)(v) << 19U) & FM_GLOBAL_RESET_CONTROL_RST_REQ_EN)
#define GFV_GLOBAL_RESET_CONTROL_RST_REQ_EN(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_CONTROL_RST_REQ_EN) >> 19U)

#define FM_GLOBAL_RESET_CONTROL_WDT2_EN  ((uint32)0xffU << 11U)
#define FV_GLOBAL_RESET_CONTROL_WDT2_EN(v) \
  (((uint32)(v) << 11U) & FM_GLOBAL_RESET_CONTROL_WDT2_EN)
#define GFV_GLOBAL_RESET_CONTROL_WDT2_EN(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_CONTROL_WDT2_EN) >> 11U)

#define FM_GLOBAL_RESET_CONTROL_WDT1_EN  ((uint32)0xffU << 3U)
#define FV_GLOBAL_RESET_CONTROL_WDT1_EN(v) \
  (((uint32)(v) << 3U) & FM_GLOBAL_RESET_CONTROL_WDT1_EN)
#define GFV_GLOBAL_RESET_CONTROL_WDT1_EN(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_CONTROL_WDT1_EN) >> 3U)

#define BM_GLOBAL_RESET_CONTROL_SEC_VIO_EN  ((uint32)0x01U << 2U)

#define BM_GLOBAL_RESET_CONTROL_SEM_EN  ((uint32)0x01U << 1U)

#define BM_GLOBAL_RESET_CONTROL_SYS_PANIC_EN  ((uint32)0x01U << 0U)

#define GLOBAL_RESET_STA_OFF  0x208U

#define FM_GLOBAL_RESET_STA_GLB_STA_LAST  ((uint32)0xffffffffU << 0U)
#define FV_GLOBAL_RESET_STA_GLB_STA_LAST(v) \
  (((uint32)(v) << 0U) & FM_GLOBAL_RESET_STA_GLB_STA_LAST)
#define GFV_GLOBAL_RESET_STA_GLB_STA_LAST(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_STA_GLB_STA_LAST) >> 0U)

#define GLOBAL_RESET_STA_ALL_OFF  0x20cU

#define FM_GLOBAL_RESET_STA_ALL_GLB_STA_ALL  ((uint32)0xffffffffU << 0U)
#define FV_GLOBAL_RESET_STA_ALL_GLB_STA_ALL(v) \
  (((uint32)(v) << 0U) & FM_GLOBAL_RESET_STA_ALL_GLB_STA_ALL)
#define GFV_GLOBAL_RESET_STA_ALL_GLB_STA_ALL(v) \
  (((uint32)(v) & FM_GLOBAL_RESET_STA_ALL_GLB_STA_ALL) >> 0U)

#define GLOBAL_ERR_STA_ALL_OFF  0x210U

#define FM_GLOBAL_ERR_STA_ALL_ERR_STA_ALL  ((uint32)0xffffffffU << 0U)
#define FV_GLOBAL_ERR_STA_ALL_ERR_STA_ALL(v) \
  (((uint32)(v) << 0U) & FM_GLOBAL_ERR_STA_ALL_ERR_STA_ALL)
#define GFV_GLOBAL_ERR_STA_ALL_ERR_STA_ALL(v) \
  (((uint32)(v) & FM_GLOBAL_ERR_STA_ALL_ERR_STA_ALL) >> 0U)

#define IST_RESET_RS_OFF  0x1000U

#define BM_IST_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_IST_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_IST_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_IST_RESET_RS_RS)
#define GFV_IST_RESET_RS_RS(v) \
  (((uint32)(v) & FM_IST_RESET_RS_RS) >> 1U)

#define BM_IST_RESET_RS_EN  ((uint32)0x01U << 0U)

#define IST_RESET_CONTROL_OFF  0x1004U

#define BM_IST_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_IST_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_IST_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define BM_IST_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_IST_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_IST_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_IST_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define MISSION_RESET_RS_OFF(n)  (0x1100U + 8U*(n))

#define BM_MISSION_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_MISSION_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_MISSION_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_MISSION_RESET_RS_RS)
#define GFV_MISSION_RESET_RS_RS(v) \
  (((uint32)(v) & FM_MISSION_RESET_RS_RS) >> 1U)

#define BM_MISSION_RESET_RS_EN  ((uint32)0x01U << 0U)

#define MISSION_RESET_CONTROL_OFF(n)  (0x1104U + (8U*(n)))

#define BM_MISSION_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_MISSION_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_MISSION_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define BM_MISSION_RESET_CONTROL_LOCK  ((uint32)0x01U << 28U)

#define BM_MISSION_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_MISSION_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_MISSION_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_MISSION_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define LATENT_RESET_RS_OFF(n)  (0x1200U + 8U*(n))

#define BM_LATENT_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_LATENT_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_LATENT_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_LATENT_RESET_RS_RS)
#define GFV_LATENT_RESET_RS_RS(v) \
  (((uint32)(v) & FM_LATENT_RESET_RS_RS) >> 1U)

#define BM_LATENT_RESET_RS_EN  ((uint32)0x01U << 0U)

#define LATENT_RESET_CONTROL_OFF(n)  (0x1204U + 8U*(n))

#define BM_LATENT_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_LATENT_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_LATENT_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define BM_LATENT_RESET_CONTROL_LOCK  ((uint32)0x01U << 28U)

#define BM_LATENT_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_LATENT_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_LATENT_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_LATENT_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define MODULE_RESET_RS_OFF(n)  (0x1300U + 8U*(n))

#define BM_MODULE_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_MODULE_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_MODULE_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_MODULE_RESET_RS_RS)
#define GFV_MODULE_RESET_RS_RS(v) \
  (((uint32)(v) & FM_MODULE_RESET_RS_RS) >> 1U)

#define BM_MODULE_RESET_RS_EN  ((uint32)0x01U << 0U)

#define MODULE_RESET_CONTROL_OFF(n)  (0x1304U + (8U*(n)))

#define BM_MODULE_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_MODULE_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_MODULE_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define FM_MODULE_RESET_CONTROL_BTI_TOUT_VAL  ((uint32)0xfU << 8U)
#define FV_MODULE_RESET_CONTROL_BTI_TOUT_VAL(v) \
  (((uint32)(v) << 8U) & FM_MODULE_RESET_CONTROL_BTI_TOUT_VAL)
#define GFV_MODULE_RESET_CONTROL_BTI_TOUT_VAL(v) \
  (((uint32)(v) & FM_MODULE_RESET_CONTROL_BTI_TOUT_VAL) >> 8U)

#define BM_MODULE_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_MODULE_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_MODULE_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_MODULE_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define CORE_RESET_RS_OFF(n)  (0x1a00U + 8U*(n))

#define BM_CORE_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_CORE_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_CORE_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_CORE_RESET_RS_RS)
#define GFV_CORE_RESET_RS_RS(v) \
  (((uint32)(v) & FM_CORE_RESET_RS_RS) >> 1U)

#define BM_CORE_RESET_RS_EN  ((uint32)0x01U << 0U)

#define CORE_RESET_CONTROL_OFF(n)  (0x1a04U + (8U*(n)))

#define BM_CORE_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_CORE_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_CORE_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define BM_CORE_RESET_CONTROL_RST_REQ_ERR_INJ  ((uint32)0x01U << 15U)

#define BM_CORE_RESET_CONTROL_WDT2_RST_ERR_INJ  ((uint32)0x01U << 14U)

#define BM_CORE_RESET_CONTROL_WDT1_RST_ERR_INJ  ((uint32)0x01U << 13U)

#define BM_CORE_RESET_CONTROL_RUN_MODE_PARITY  ((uint32)0x01U << 12U)

#define FM_CORE_RESET_CONTROL_BTI_TOUT_VAL  ((uint32)0xfU << 8U)
#define FV_CORE_RESET_CONTROL_BTI_TOUT_VAL(v) \
  (((uint32)(v) << 8U) & FM_CORE_RESET_CONTROL_BTI_TOUT_VAL)
#define GFV_CORE_RESET_CONTROL_BTI_TOUT_VAL(v) \
  (((uint32)(v) & FM_CORE_RESET_CONTROL_BTI_TOUT_VAL) >> 8U)

#define BM_CORE_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_CORE_RESET_CONTROL_RST_REQ_EN  ((uint32)0x01U << 5U)

#define BM_CORE_RESET_CONTROL_WDT2_RST_EN  ((uint32)0x01U << 4U)

#define BM_CORE_RESET_CONTROL_WDT1_RST_EN  ((uint32)0x01U << 3U)

#define BM_CORE_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_CORE_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_CORE_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define DBG_RESET_RS_OFF  0x1b00U

#define BM_DBG_RESET_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_DBG_RESET_RS_RS  ((uint32)0xfU << 1U)
#define FV_DBG_RESET_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_DBG_RESET_RS_RS)
#define GFV_DBG_RESET_RS_RS(v) \
  (((uint32)(v) & FM_DBG_RESET_RS_RS) >> 1U)

#define BM_DBG_RESET_RS_EN  ((uint32)0x01U << 0U)

#define DBG_RESET_CONTROL_OFF  0x1b04U

#define BM_DBG_RESET_CONTROL_RMON_O  ((uint32)0x01U << 31U)

#define BM_DBG_RESET_CONTROL_RMON_I  ((uint32)0x01U << 30U)

#define BM_DBG_RESET_CONTROL_RSTA  ((uint32)0x01U << 29U)

#define BM_DBG_RESET_CONTROL_DBG_REQ_EN  ((uint32)0x01U << 8U)

#define BM_DBG_RESET_CONTROL_AUTO_CLR_RST_B  ((uint32)0x01U << 6U)

#define BM_DBG_RESET_CONTROL_SLP_MODE  ((uint32)0x01U << 2U)

#define BM_DBG_RESET_CONTROL_HIB_MODE  ((uint32)0x01U << 1U)

#define BM_DBG_RESET_CONTROL_RUN_MODE  ((uint32)0x01U << 0U)

#define SW_RESET_PASSWORD_CONTROL_OFF  0x1c00U

#define BM_SW_RESET_PASSWORD_CONTROL_LOCK  ((uint32)0x01U << 31U)

#define BM_SW_RESET_PASSWORD_CONTROL_EN  ((uint32)0x01U << 0U)

#define SW_RESET_PASSWORD_OFF  0x1c04U

#define FM_SW_RESET_PASSWORD_PW  ((uint32)0xffffffffU << 0U)
#define FV_SW_RESET_PASSWORD_PW(v) \
  (((uint32)(v) << 0U) & FM_SW_RESET_PASSWORD_PW)
#define GFV_SW_RESET_PASSWORD_PW(v) \
  (((uint32)(v) & FM_SW_RESET_PASSWORD_PW) >> 0U)

#define GENERAL_REG_RS_OFF(n)  (0x2000U + 8U*(n))

#define BM_GENERAL_REG_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_GENERAL_REG_RS_RS  ((uint32)0xfU << 1U)
#define FV_GENERAL_REG_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_GENERAL_REG_RS_RS)
#define GFV_GENERAL_REG_RS_RS(v) \
  (((uint32)(v) & FM_GENERAL_REG_RS_RS) >> 1U)

#define BM_GENERAL_REG_RS_EN  ((uint32)0x01U << 0U)

#define GENERAL_REG_OFF(n)  (0x2004U + (8U*(n)))

#define FM_GENERAL_REG_GENERAL  ((uint32)0xffffffffU << 0U)
#define FV_GENERAL_REG_GENERAL(v) \
  (((uint32)(v) << 0U) & FM_GENERAL_REG_GENERAL)
#define GFV_GENERAL_REG_GENERAL(v) \
  (((uint32)(v) & FM_GENERAL_REG_GENERAL) >> 0U)

#define BOOT_MODE_RS_OFF  0x3000U

#define BM_BOOT_MODE_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_BOOT_MODE_RS_RS  ((uint32)0xfU << 1U)
#define FV_BOOT_MODE_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_BOOT_MODE_RS_RS)
#define GFV_BOOT_MODE_RS_RS(v) \
  (((uint32)(v) & FM_BOOT_MODE_RS_RS) >> 1U)

#define BM_BOOT_MODE_RS_EN  ((uint32)0x01U << 0U)

#define BOOT_MODE_OFF  0x3004U

#define FM_BOOT_MODE_BOOT_MODE  ((uint32)0x7fU << 0U)
#define FV_BOOT_MODE_BOOT_MODE(v) \
  (((uint32)(v) << 0U) & FM_BOOT_MODE_BOOT_MODE)
#define GFV_BOOT_MODE_BOOT_MODE(v) \
  (((uint32)(v) & FM_BOOT_MODE_BOOT_MODE) >> 0U)

#define RESET_FLOW_TIME_RS_OFF  0x3100U

#define BM_RESET_FLOW_TIME_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RESET_FLOW_TIME_RS_RS  ((uint32)0xfU << 1U)
#define FV_RESET_FLOW_TIME_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RESET_FLOW_TIME_RS_RS)
#define GFV_RESET_FLOW_TIME_RS_RS(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_RS_RS) >> 1U)

#define BM_RESET_FLOW_TIME_RS_EN  ((uint32)0x01U << 0U)

#define RESET_FLOW_TIME_CONTROL_OFF  0x3104U

#define FM_RESET_FLOW_TIME_CONTROL_T4  ((uint32)0x1fU << 23U)
#define FV_RESET_FLOW_TIME_CONTROL_T4(v) \
  (((uint32)(v) << 23U) & FM_RESET_FLOW_TIME_CONTROL_T4)
#define GFV_RESET_FLOW_TIME_CONTROL_T4(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_CONTROL_T4) >> 23U)

#define FM_RESET_FLOW_TIME_CONTROL_T3  ((uint32)0x1fU << 18U)
#define FV_RESET_FLOW_TIME_CONTROL_T3(v) \
  (((uint32)(v) << 18U) & FM_RESET_FLOW_TIME_CONTROL_T3)
#define GFV_RESET_FLOW_TIME_CONTROL_T3(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_CONTROL_T3) >> 18U)

#define FM_RESET_FLOW_TIME_CONTROL_T2  ((uint32)0xffU << 10U)
#define FV_RESET_FLOW_TIME_CONTROL_T2(v) \
  (((uint32)(v) << 10U) & FM_RESET_FLOW_TIME_CONTROL_T2)
#define GFV_RESET_FLOW_TIME_CONTROL_T2(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_CONTROL_T2) >> 10U)

#define FM_RESET_FLOW_TIME_CONTROL_T1  ((uint32)0x1fU << 5U)
#define FV_RESET_FLOW_TIME_CONTROL_T1(v) \
  (((uint32)(v) << 5U) & FM_RESET_FLOW_TIME_CONTROL_T1)
#define GFV_RESET_FLOW_TIME_CONTROL_T1(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_CONTROL_T1) >> 5U)

#define FM_RESET_FLOW_TIME_CONTROL_T0  ((uint32)0x1fU << 0U)
#define FV_RESET_FLOW_TIME_CONTROL_T0(v) \
  (((uint32)(v) << 0U) & FM_RESET_FLOW_TIME_CONTROL_T0)
#define GFV_RESET_FLOW_TIME_CONTROL_T0(v) \
  (((uint32)(v) & FM_RESET_FLOW_TIME_CONTROL_T0) >> 0U)

#define RSTGEN_RES_RS_OFF  0x3200U

#define BM_RSTGEN_RES_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_RES_RS_RS  ((uint32)0xfU << 1U)
#define FV_RSTGEN_RES_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RSTGEN_RES_RS_RS)
#define GFV_RSTGEN_RES_RS_RS(v) \
  (((uint32)(v) & FM_RSTGEN_RES_RS_RS) >> 1U)

#define BM_RSTGEN_RES_RS_EN  ((uint32)0x01U << 0U)

#define RSTGEN_RES_OFF  0x3204U

#define FM_RSTGEN_RES_RES  ((uint32)0xffffffffU << 0U)
#define FV_RSTGEN_RES_RES(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_RES_RES)
#define GFV_RSTGEN_RES_RES(v) \
  (((uint32)(v) & FM_RSTGEN_RES_RES) >> 0U)

#define RSTGEN_MISC_RS_OFF  0x3300U

#define BM_RSTGEN_MISC_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_MISC_RS_RS  ((uint32)0xfU << 1U)
#define FV_RSTGEN_MISC_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RSTGEN_MISC_RS_RS)
#define GFV_RSTGEN_MISC_RS_RS(v) \
  (((uint32)(v) & FM_RSTGEN_MISC_RS_RS) >> 1U)

#define BM_RSTGEN_MISC_RS_EN  ((uint32)0x01U << 0U)

#define RSTGEN_MISC_OFF  0x3304U

#define FM_RSTGEN_MISC_MISC  ((uint32)0xffffffffU << 0U)
#define FV_RSTGEN_MISC_MISC(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_MISC_MISC)
#define GFV_RSTGEN_MISC_MISC(v) \
  (((uint32)(v) & FM_RSTGEN_MISC_MISC) >> 0U)

#define RSTGEN_SUP_DOM_OFF  0x3400U

#define BM_RSTGEN_SUP_DOM_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_SUP_DOM_PPROT  ((uint32)0x3U << 5U)
#define FV_RSTGEN_SUP_DOM_PPROT(v) \
  (((uint32)(v) << 5U) & FM_RSTGEN_SUP_DOM_PPROT)
#define GFV_RSTGEN_SUP_DOM_PPROT(v) \
  (((uint32)(v) & FM_RSTGEN_SUP_DOM_PPROT) >> 5U)

#define BM_RSTGEN_SUP_DOM_SEC_EN  ((uint32)0x01U << 4U)

#define FM_RSTGEN_SUP_DOM_DID  ((uint32)0xfU << 0U)
#define FV_RSTGEN_SUP_DOM_DID(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_SUP_DOM_DID)
#define GFV_RSTGEN_SUP_DOM_DID(v) \
  (((uint32)(v) & FM_RSTGEN_SUP_DOM_DID) >> 0U)

#define RSTGEN_TOUT_RS_OFF  0x3500U

#define BM_RSTGEN_TOUT_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_TOUT_RS_RS  ((uint32)0xfU << 1U)
#define FV_RSTGEN_TOUT_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RSTGEN_TOUT_RS_RS)
#define GFV_RSTGEN_TOUT_RS_RS(v) \
  (((uint32)(v) & FM_RSTGEN_TOUT_RS_RS) >> 1U)

#define BM_RSTGEN_TOUT_RS_EN  ((uint32)0x01U << 0U)

#define RSTGEN_IST_TOUT_OFF  0x3504U

#define FM_RSTGEN_IST_TOUT_TOUT_VAL  ((uint32)0xffffU << 0U)
#define FV_RSTGEN_IST_TOUT_TOUT_VAL(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_IST_TOUT_TOUT_VAL)
#define GFV_RSTGEN_IST_TOUT_TOUT_VAL(v) \
  (((uint32)(v) & FM_RSTGEN_IST_TOUT_TOUT_VAL) >> 0U)

#define RSTGEN_BTI_TOUT_OFF  0x3508U

#define FM_RSTGEN_BTI_TOUT_TOUT_VAL  ((uint32)0xffffU << 0U)
#define FV_RSTGEN_BTI_TOUT_TOUT_VAL(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_BTI_TOUT_TOUT_VAL)
#define GFV_RSTGEN_BTI_TOUT_TOUT_VAL(v) \
  (((uint32)(v) & FM_RSTGEN_BTI_TOUT_TOUT_VAL) >> 0U)

#define RSTGEN_FUSA_RS_OFF  0x4000U

#define BM_RSTGEN_FUSA_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_FUSA_RS_RS  ((uint32)0xfU << 1U)
#define FV_RSTGEN_FUSA_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RSTGEN_FUSA_RS_RS)
#define GFV_RSTGEN_FUSA_RS_RS(v) \
  (((uint32)(v) & FM_RSTGEN_FUSA_RS_RS) >> 1U)

#define BM_RSTGEN_FUSA_RS_EN  ((uint32)0x01U << 0U)

#define BM_RSTGEN_APB_ERR_INT_OFF  0x4004U

#define RSTGEN_FUSA_INT_OFF  0x400cU

#define BM_RSTGEN_FUSA_INT_BTI_TOUT_ERR_CLR  ((uint32)0x01U << 21U)

#define BM_RSTGEN_FUSA_INT_SWMM_CLR  ((uint32)0x01U << 20U)

#define BM_RSTGEN_FUSA_INT_SYNC_ERR_CLR  ((uint32)0x01U << 19U)

#define BM_RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_CLR  ((uint32)0x01U << 18U)

#define BM_RSTGEN_FUSA_INT_SWM_TRANS_ERR_CLR  ((uint32)0x01U << 17U)

#define BM_RSTGEN_FUSA_INT_SWM_CHK_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_RSTGEN_FUSA_INT_BTI_TOUT_ERR_STA  ((uint32)0x01U << 13U)

#define BM_RSTGEN_FUSA_INT_SWMM_STA  ((uint32)0x01U << 12U)

#define BM_RSTGEN_FUSA_INT_SYNC_ERR_STA  ((uint32)0x01U << 11U)

#define BM_RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_STA  ((uint32)0x01U << 10U)

#define BM_RSTGEN_FUSA_INT_SWM_TRANS_ERR_STA  ((uint32)0x01U << 9U)

#define BM_RSTGEN_FUSA_INT_SWM_CHK_ERR_STA  ((uint32)0x01U << 8U)

#define BM_RSTGEN_FUSA_INT_BTI_TOUT_ERR_EN  ((uint32)0x01U << 5U)

#define BM_RSTGEN_FUSA_INT_SWMM_EN  ((uint32)0x01U << 4U)

#define BM_RSTGEN_FUSA_INT_SYNC_ERR_EN  ((uint32)0x01U << 3U)

#define BM_RSTGEN_FUSA_INT_BOOT_MODE_CHK_ERR_EN  ((uint32)0x01U << 2U)

#define BM_RSTGEN_FUSA_INT_SWM_TRANS_ERR_EN  ((uint32)0x01U << 1U)

#define BM_RSTGEN_FUSA_INT_SWM_CHK_ERR_EN  ((uint32)0x01U << 0U)

#define BM_RSTGEN_WDT_LKSTEP_INT_OFF  0x4010U

#define BM_WDT_LKSTEP_INT_IST_TOUT_ERR_INT_CLR  ((uint32)0x01U << 18U)

#define BM_WDT_LKSTEP_INT_IST_TOUT_ERR_INT_STA  ((uint32)0x01U << 10U)

#define BM_WDT_LKSTEP_INT_IST_TOUT_ERR_INT_EN  ((uint32)0x01U << 2U)

#define RSTGEN_WDAT_ERR_INJ_OFF  0x4100U

#define RSTGEN_WECC_ERR_INJ_OFF  0x4104U

#define RSTGEN_PRDATAINJ_OFF  0x4108U

#define RSTGEN_REG_PARITY_ERR_INT_STAT_OFF  0x410cU

#define RSTGEN_REG_PARITY_ERR_INT_SIG_EN_OFF  0x4110U

#define BM_RSTGEN_ERR_INJ_EN_OFF  0x4114U

#define BM_RSTGEN_ERR_INJ_BIT_OFF  0x4118U

#define BM_RSTGEN_SELFTEST_MODE_OFF  0x411cU

#define RSTGEN_FUNC_INT_RS_OFF  0x4200U

#define BM_RSTGEN_FUNC_INT_RS_LOCK  ((uint32)0x01U << 31U)

#define FM_RSTGEN_FUNC_INT_RS_RS  ((uint32)0xfU << 1U)
#define FV_RSTGEN_FUNC_INT_RS_RS(v) \
  (((uint32)(v) << 1U) & FM_RSTGEN_FUNC_INT_RS_RS)
#define GFV_RSTGEN_FUNC_INT_RS_RS(v) \
  (((uint32)(v) & FM_RSTGEN_FUNC_INT_RS_RS) >> 1U)

#define BM_RSTGEN_FUNC_INT_RS_EN  ((uint32)0x01U << 0U)

#define RSTGEN_FUNC_INT_OFF  0x4204U

#define BM_RSTGEN_FUNC_INT_ACCESS_PER_ERR_CLR  ((uint32)0x01U << 16U)

#define BM_RSTGEN_FUNC_INT_ACCESS_PER_ERR_STA  ((uint32)0x01U << 8U)

#define BM_RSTGEN_FUNC_INT_ACCESS_PER_ERR_EN  ((uint32)0x01U << 0U)

#define RSTGEN_RO_MISC_OFF  0x4208U

#define FM_RSTGEN_RO_MISC_MISC_RO  ((uint32)0xffffffffU << 0U)
#define FV_RSTGEN_RO_MISC_MISC_RO(v) \
  (((uint32)(v) << 0U) & FM_RSTGEN_RO_MISC_MISC_RO)
#define GFV_RSTGEN_RO_MISC_MISC_RO(v) \
  (((uint32)(v) & FM_RSTGEN_RO_MISC_MISC_RO) >> 0U)


#define RSTGEN_POLLs    (30000U)
/********************************************************************************************************
 *                                  Global Function Declarations                                        *
 *******************************************************************************************************/

/** *****************************************************************************************************
 * \brief rstgen core control
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_RstgenLldCoreControl(uint32 base, uint32 coreIdx, boolean en)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      coreIdx - core id
 *                      en - 0: off, 1: on
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 0 if OK, or a error code.
 *
 * Description        : rstgen core control
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_RstgenLldCoreControl(uint32 base, uint32 coreIdx, boolean en);

/** *****************************************************************************************************
 * \brief rstgen core reset
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_RstgenLldCoreReset(uint32 base, uint32 coreIdx)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      coreIdx - core id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 0 if OK, or a error code.
 *
 * Description        : rstgen core reset
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_RstgenLldCoreReset(uint32 base, uint32 coreIdx);

/** *****************************************************************************************************
 * \brief rstgen module control
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_RstgenLldModuleControl(uint32 base, uint32 moduleIdx, boolean en)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      moduleIdx - module index
 *                      en - 0:module off, 1:module on
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 0 if OK, or a error code.
 *
 * Description        : rstgen module control
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_RstgenLldModuleControl(uint32 base, uint32 moduleIdx, boolean en);

/** *****************************************************************************************************
 * \brief rstgen mission control
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_RstgenLldMissionControl(uint32 base, uint32 missionIdx, boolean en)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      missionIdx - mission index
 *                      en - 0:misson off, 1:misson on
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 0 if OK, or a error code.
 *
 * Description        : rstgen mission control
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_RstgenLldMissionControl(uint32 base, uint32 missionIdx, boolean en);

/** *****************************************************************************************************
 * \brief rstgen debug control
 *
 * \verbatim
 * Syntax             : Std_ReturnType Mcu_Ip_RstgenLldDebugControl(uint32 base, boolean en)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      en - 0:debug off, 1:debug on
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 0 if OK, or a error code.
 *
 * Description        : rstgen debug control
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
Std_ReturnType Mcu_Ip_RstgenLldDebugControl(uint32 base, boolean en);
/** *****************************************************************************************************
 * \brief global reset
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_RstgenLldGlobalReset(uint32 sfBase)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : sfBase - RSTGEN base address.
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : global reset, sf send sw global reset req, need lp set rst_req_en
 *
 * \endverbatim
 * Traceability       : SW_SM005
 *******************************************************************************************************/
void Mcu_Ip_RstgenLldGlobalReset(uint32 sfBase);

/** *****************************************************************************************************
 * \brief rstgen get core reset status
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_RstgenLldGetCoreResetStatus(uint32 base, uint32 coreIdx)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      coreIdx - core index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 1, the core reset has be released.
 *                      0, the core reset hasn't be released.
 *
 * Description        : rstgen get core reset status
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_RstgenLldGetCoreResetStatus(uint32 base, uint32 coreIdx);

/** *****************************************************************************************************
 * \brief rstgen get module reset status
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_RstgenLldGetModuleResetStatus(uint32 base, uint32 moduleIdx)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      moduleIdx - module index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 1, the module reset has be released.
 *                      0, the module reset hasn't be released.
 *
 * Description        : rstgen get module reset status
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_RstgenLldGetModuleResetStatus(uint32 base, uint32 moduleIdx);

/** *****************************************************************************************************
 * \brief rstgen get mission reset status
 *
 * \verbatim
 * Syntax             : boolean Mcu_Ip_RstgenLldGetMissionResetStatus(uint32 base, uint32 missionIdx)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      missionIdx - mission index
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : 1, the mission reset has be released.
 *                      0, the mission reset hasn't be released.
 *
 * Description        : rstgen get mission reset status
 * \endverbatim
 *******************************************************************************************************/
boolean Mcu_Ip_RstgenLldGetMissionResetStatus(uint32 base, uint32 missionIdx);

/** *****************************************************************************************************
 * \brief rstgen get general reg value
 *
 * \verbatim
 * Syntax             : uint32 Mcu_Ip_RstgenLldReadGeneralReg(uint32 base, uint32 regIdx)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      regIdx - general register id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : general reg value
 *
 * Description        : rstgen get general reg value
 * \endverbatim
 *******************************************************************************************************/
uint32 Mcu_Ip_RstgenLldReadGeneralReg(uint32 base, uint32 regIdx);

/** *****************************************************************************************************
 * \brief rstgen write general reg value
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_RstgenLldWriteGeneralReg(uint32 base, uint32 regIdx, uint32 val)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - RSTGEN base address.
 *                      regIdx - general register id
 *                      val - value to write
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function Write general register value.
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_RstgenLldWriteGeneralReg(uint32 base, uint32 regIdx, uint32 val);

/** *****************************************************************************************************
 * \brief This function write global reset mask.
 *
 * \verbatim
 * Syntax             : void Mcu_Ip_RstgenRgGlbResetEn(uint32 base, uint32 msk)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base - rstgen base
 *                      msk - value to write
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function write global reset mask.
 * \endverbatim
 *******************************************************************************************************/
void Mcu_Ip_RstgenRgGlbResetEn(uint32 base, uint32 msk);

/** *****************************************************************************************************
 * \brief read the reset type from the hardware register
 *
 * \verbatim
 * Syntax             : Mcu_RawResetType Mcu_Ip_GetResetRawValue(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Reentrant
 *
 * Parameters (in)    : base - RSTGEN base address
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : Reset raw value
 *
 * Description        : read the reset type from the hardware register
 * \endverbatim
 *******************************************************************************************************/
Mcu_RawResetType Mcu_Ip_GetResetRawValue(uint32 base);

/** *****************************************************************************************************
 * \brief get reset type
 *
 * \verbatim
 * Syntax             : Mcu_ResetType Mcu_Ip_GetResetReason(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Reentrant
 *
 * Parameters (in)    : None
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : reset type
 *
 * Description        : get reset type
 * \endverbatim
 *******************************************************************************************************/
Mcu_ResetType Mcu_Ip_GetResetReason(uint32 base);

#endif /* MCU_RSTGEN_H */
/* End of file */
